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ADM1075
Pin No.
Data Sheet
TSSOP
14
LFCSP
10
Mnemonic
SHDN
Description
Drive this pin low to shut down the gate. Internal weak pull-up to VIN.
This pin is also used to configure the desired retry scheme. See the Hot Swap Fault Retry section for
additional details.
15
16
11
12
RESTART
GPO1/ALERT1
/CONV
Falling Edge Triggered 10 sec Automatic Restart. The gate remains off for 10 seconds, and then
powers back up. Internal weak pull-up to VIN. This pin is also used to configure the desired retry
scheme. See the Hot Swap Fault Retry section for additional details.
General-Purpose Digital Output (GPO1).
Alert (ALERT1). This pin can be configured to generate an alert signal when one or more fault or
warning conditions have been detected.
Conversion (CONV). This pin can be used as an input signal to control when a power monitor ADC
sampling cycle begins.
This pin defaults to indicate FET health mode at power-up. There is no internal pull-up on this pin.
17
13
GPO2/ALERT2
General-Purpose Digital Output (GPO2).
Alert (ALERT2). This pin can be configured to generate an alert signal when one or more fault or
warning conditions have been detected.
This pin is also used to configure the desired retry scheme. See the Hot Swap Fault Retry section for
further details. This pin defaults to indicate a seven-attempt fail at power-up.
There is no internal pull-up on this pin.
18
19
20
21
22
23
24
25
14
15
16
17
18
19
20
21
SDAO
SDAI
SCL
PWRGD
ADC_AUX
SPLYGD
VEE
SENSE?
PMBus Serial Data Output. This is a split version of the SDA for easy use with optocouplers.
PMBus Serial Data Input. This is a split version of the SDA for easy use with optocouplers.
PMBus Clock Pin. Open-drain input requires an external resistive pull-up.
Power-Good Signal. This pin is used to indicate that the FET is no longer in the linear region and
capacitors are fully charged. See the PWRGD section for details on assert and deassert.
This pin is used to read back a voltage using the internal ADC.
This pin asserts low when the supply is within the UV and OV limits set by the UVx and OV pins.
Chip Ground Pin. Must connect to –VIN rail (lowest potential).
Negative Current Sense Input Pin. A sense resistor between the SENSE+ pin and the SENSE? pin sets
the analog current limit. The hot swap operation controls the external FET gate to maintain the
(V SENSE+ ? V SENSE? ) sense voltage. This pin also connects to the VEE node, but should be routed
separately.
26
22
SENSE+
Positive Current Sense Input Pin. A sense resistor between the SENSE+ pin and the SENSE? pin sets
the analog current limit. The hot swap operation controls the external FET gate to maintain the
(V SENSE+ ? V SENSE? ) sense voltage. This pin also connects to the FET source node.
27
23
GATE
Gate Output Pin. This pin is the gate drive of an external N-channel FET. It is driven by the FET drive
controller. The FET drive controller regulates to a maximum load current by regulating the GATE pin.
GATE is held low while the supply is out of the voltage range.
28
24
EPAD
VEE_G
EPAD
Chip Ground Pin. Must connect to –VIN rail (lowest potential). The PCB layout should configure this
pin as the gate pull-down return.
Exposed Pad. Solder the exposed pad to the board to improve thermal dissipation. The exposed pad
can be connected to VEE.
Rev. C | Page 12 of 52
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